1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory. More particularly, but not by way of limitation, the present invention relates to a voltage regulator and a voltage regulation method associated with a voltage that is applied to a control gate of a memory cell transistor and accumulated in a floating gate of the memory cell.
2. Description of the Related Art
Information processing apparatuses such as a portable multimedia player, computer, etc. tend to require high speed operation and large capacity in semiconductor memory devices employed therein.
A semiconductor memory device may be classified as a volatile semiconductor memory device or a nonvolatile semiconductor memory device. The volatile semiconductor memory device classification includes dynamic random access memory (DRAM) and static random access memory (SRAM). Volatile semiconductor memory devices have fast read and write speed, but contents stored in such a memory cell are lost when an external power supply is cut off.
The nonvolatile semiconductor memory device classification includes mask read only memory (MROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), and electrically erasable programmable read-only memory (EEPROM).
Such nonvolatile semiconductor memory devices have been typically used to store contents that must be preserved even when an external power supply is cut off. It is not easy to erase or re-program MROM, PROM, and EPROM devices from host system. Erase and write operations can be more easily performed in EEPROM by a host system.
Many electronic devices require high density EEPROM. Moreover, a data storage device such as a digital camera etc. is required to be compact in the size. In using a hard disk device having a rotary magnetic disk as an auxiliary memory device in a battery-power computer system based on a portable computer or notebook computer size, it needs to occupy a relatively wide area, thus designers of these systems are very interested in a development of EEPROM occupying a relatively smaller area and having a relatively higher density and higher performance.
Flash EEPROM having a flash erase function have been developed. The flash EEPROM may be a NAND, NOR or AND type, depending upon how memory cell arrays are configured. For example, a memory cell array of a typical NOR-type flash EEPROM comprises bit lines for providing and receiving data with memory cell transistors, and word lines that form a matrix with the bit lines to control gates of the memory cell transistors.
Each memory cell transistor of the NOR memory cell array is constructed of a MOS transistor having a floating gate formed by interposing a gate oxide in a channel region between source and drain regions and a control gate formed on the floating gate through an interlayer insulation layer. In operation, a program voltage is applied to the control gate CG and is accumulated in the floating gate FG.
A nonvolatile semiconductor memory device having such memory cell has various operating modes, for example, program (write), erase, read, program verify and erase verify. In each of these operating modes, voltage applied to the control gate of the memory cell transistor may be a high voltage level output from a high voltage pumping circuit.
An example for a voltage regulator in such nonvolatile semiconductor memory device is disclosed in U.S. Pat. No. 5,835,420 published on Nov. 10, 1998.
In a NOR type flash memory cell, a single level cell storing a single bit may be changed into a multilevel cell (MLC) storing multiple bits. In this instance, the effects of a read voltage level on a sensing margin increase. That is, when the read voltage level is stabilized, the sensing margin can increase. Conversely, when the read voltage is unstable, the sensing margin decreases, causing read error.
FIG. 1 is a block diagram of a voltage supplier in a nonvolatile semiconductor memory according to the conventional art. Referring to FIG. 1, there is shown a voltage supplier comprising a control circuit 400, an oscillator 200, a high voltage pump 100 and a regulator 300.
The control circuit 400 generates an oscillating enable signal Osc_Enable and an Active signal in response to first and second detection signals too_low and too_high from the regulator 300. The oscillator 200 performs an oscillation in response to the oscillating enable signal Osc_Enable and generates a pumping clock Pump_Clk. The high voltage pump 100 performs charge pumping in response to the pumping clock Pump_Clk, and outputs a voltage on node ND1. The regulator 300 detects a level of the voltage on node ND1, generates the first and second detection signals too_low and too_high, and receives the Active signal provided by the control circuit 400. A terminal Vwl_read of the regulator 300 is the same as the node ND1, and becomes a detection terminal and also a voltage output terminal.
FIG. 2 is a circuit diagram of the regulator in FIG. 1, according to the conventional art. FIG. 3 is a timing diagram for signals identified in FIG. 2.
Referring first to FIG. 2, a regulator 300 includes a standby regulating unit 321 and an active regulating unit 331. The regulator 300 detects the output of the high voltage pump 100 at detection output terminal Vwl_read, and maintains the output of the high voltage pump 100 using a reference voltage Vref. When the regulator 300 outputs the too_low detection signal, the control circuit 400 outputs the Active signal. As shown in FIG. 3, the Active signal has a phase opposite to that of the Standby signal that is internal to the Regulator 300. Accordingly, the standby regulating unit 321 and the active regulating unit 331 alternately perform a voltage regulating operation.
A time constant RC value based on resistances R0 and R1 of the standby regulating unit 321 is greater than a time constant RC value based on resistances R100 and R101 of the active regulating unit 331 to substantially reduce standby current Isb. The ratio of the resistance values in the standby regulating unit 321 is the same as the ratio of the resistance values in the active regulating unit 331 (i.e., R0/R1=R100/R101). But the total resistance value in the standby regulating unit 321 is much greater than total resistance value in the active regulating unit 331 (i.e., (R0+R1)>>(R100+R101)). Thus, a response speed of the standby regulating unit 321 is slower than that of the active regulating unit 331.
For example, in a section between time points t1 and t2 of FIG. 3, when the Active signal is disabled, a voltage level of detection output terminal Vwl_read starts to gradually fall towards a first level L1 by a leakage current [Ileak (Ileak>>Isb)]. At this time, the standby regulating unit 321 is enabled and so it operates until detecting a low signal too_low. When the voltage level of the detection output terminal Vwl_read falls to the first level L1, a voltage level of a first divided-voltage detection output terminal Node_A becomes lower than a level of the predetermined reference voltage Vref, and a comparator OPA0 outputs a first detection signal, the low signal too_low, which requires a voltage level increase of the detection output terminal Vwl_read. The control circuit 400 enables the Active signal when the signal too_low is received. At this time, the high voltage pump 100 of FIG. 1 also performs a charge pumping operation. When the active regulating unit 331 is enabled and starts to operate, a PMOS transistor MP1 is turned off, and an inverter INV0 inverts a Standby signal to be at a logic low level, and PMOS transistor MP0 is turned on. A turn-on operation of the PMOS transistor MP0 applies a power voltage VDD to the first divided-voltage detection output terminal Node_A until the comparator OPAL of the active regulating unit 331 detects a signal too_high. As a result, at a section of from time points t2 to t3 of FIG. 3, the active regulating unit 331 is enabled until the too_high signal is generated as a logic high level after a time point t3. After that, the PMOS transistor MP0 is turned off, and the initialization operation of the first divided-voltage detection output terminal Node_A is stopped. When the too_high signal is applied to the control circuit 400, the Active signal is disabled, and the Standby signal is enabled. At this time, to initialize a voltage level of a second divided-voltage detection output terminal B to a level of operation power voltage VDD, the PMOS transistor MP1 is turned on.
The standby regulating unit 321 and the active regulating unit 331 operate alternately as shown in FIG. 3. After time point t6, however, assume that a read command is applied. In this instance, the Active signal is enabled for an extended time T1 and the Standby signal is disabled during time T1. As a result, the operation of the standby regulating unit 321 is delayed, and a voltage on detection terminal Vwl_read may drop below level L1 as illustrated by marker P1 in FIG. 3. This problem may decrease read margin when a voltage level of the detection output terminal Vwl_read is applied to a word line in a read operating mode.
Therefore it is first of all important to develop a regulating technique to supply a required precise and stable voltage in an operating mode of a nonvolatile semiconductor memory, for example during a read operation.